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Texas Instruments LMK0482x Ultra-Low-Noise Synthesizer and Jitter Cleaner high-performance with JEDEC JESD204B support. The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using the device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems. Features include the ability to trade-off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay. These features make the LMK0482x family ideal for providing flexible high-performance clocking trees. The LMK0482x-EP devices feature gold bond wires, a temperature range of -55°C to +105°C, and include an SnPb lead finish.
Features
JEDEC JESD204B support
Ultra-low RMS jitter
88fs RMS jitter (12kHz to 20MHz)
91fs RMS jitter (100Hz to 20MHz)
-162.5dBc/Hz noise floor at 245.76MHz
Up to 14 differential device clocks from PLL2
Up to 7 SYSREF clocks
3.1GHz Maximum clock output frequency
LVPECL, LVDS, HSDS, and LCPECL
Programmable outputs from PLL2
Up to 1 buffered VCXO/crystal output from PLL1, LVPECL, LVDS, 2xLVCMOS programmable
Dual loop PLLatinum™ PLL architecture
PLL1
Up to 3 redundant input clocks
Automatic and manual switch-over modes
Hitless switching and LOS
Integrated low-noise crystal oscillator circuit
Holdover mode when input clocks are lost
PLL2
Normalized (1Hz) PLL noise floor of -227dBc/Hz
Phase detector rate up to 155MHz
OSCin frequency-doubler
Two integrated low-noise VCOs
50% duty cycle output divides, 1 to 32 (even and odd)
Precision digital delay, dynamically adjustable
25ps step analog delay
Multi-mode: dual PLL, single PLL, and clock distribution
Industrial -40°C to +85°C temperature range
Supports +105°C PCB temperature (measured at thermal pad)
